download Altera Quartus Prime 15.1 Design x64 (Pro Edition / Standart Edition)
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Altera Company announced a new version of the design tools – 15.1. This version starts the new generation of CAD Quartus series – Quartus Prime. The core of the new Quartus Prime was a software tool Spectra-Q Engine, which allows to significantly simplify and accelerate the design process. Application of Spectra-Q Engine allows you to:
In times to reduce compilation time by using advanced algorithms, optimization and distributed incremental compilation;
In order to reduce the number of iterations in the design through the use of new tools and hierarchical route design;
Significantly accelerate the commissioning of the project by raising the level of abstraction.
The new facility BluePrint Platform Designer, which is part of Spectra-Q Engine, provides a user-friendly interface management, and I / O blocks designed device, performing assigned and verified in real time. This approach eliminates the need to spend time on the recompilation of the project to verify the correct execution of assignments, as well as the need for analysis of complex, error messages in the event of incorrect assignment. Application BluePrint Platform Designer allows an order to reduce the time for implementation of the interfaces in the project. Altera offers a presentation to review the BluePrint Platform Designer, as well as free online training on this tool.
With the Spectra-Q Engine time analyzer TimeQuest Timing Analyzer has become a part of it. Through the application of new, more sophisticated algorithms, timing analysis in Quatus Prime v15.1 performed twice as fast. Also in the Spectra-Q Engine include new means of placing the draft elements on a chip VLSI SP – Hybrid Placer, using new placement algorithms. It simplifies the process of optimizing and making it more predictable.
Spectra-Q Engine gives developers a lot of design input options: in addition to the traditional input project using HDL-description (VHDL languages, Verilog, System Verilog), a user is given a high-level design entry using three basic approaches:
The implementation of the mathematical model of the device in Matlab / Simulink and its subsequent translation in HDL means Altera DSP Builder. This approach is focused on the development of devices treating an digital signals.
The implementation on VLSI SP hardware accelerators to the host processor in accordance with the OpenCL standard using Altera OpenCL SDK. Development is done in C language using OpenCL extensions that provide computing parallelism developed by the user code using the SDK OpenCL automatically translated into VLSI design for the submarine. This approach involves the joint use of VLSI submarines from the host processor. In the role of host may act as an external processor, and built-in processor system from the chip Altera SoC.
Development of the device in high-level languages - C / C ++ using the new means of high-level synthesis (HLS – High Level Synthesis) – A ++ Compiler. The approach is generic, but at this time A ++ Compiler is in development.
Altera offers available with the press release on the Spectra-Q Engine, as well as receive training on the application of Spectra-Q in Quartus Prime.
The Quartus Prime v15.1 extends support families MAX 10 and Arria 10. For most chips are final timing models and consumption patterns. In general, support for families in VLSI SP Altera Quartus Prime v15.1 has not changed in comparison with the Quartus II v15.0. It supported family include:
MAX II, MAX V, MAX 10;
Cyclone IV, Cyclone V;
Arria II, Arria II GZ, Arria V, Arria V GZ, Arria 10;
Startix IV, Stratix V.
In contrast to the Quartus II Quartus Prime will be released in three versions:
Quartus Prime Lite Edition (similar to the Quartus II Web Edition);
Quartus Prime Standard Edition (similar Quartus II Subscription Edition);
Quartus Prime Pro Edition, designed exclusively to work with the family of Arria 10 (and in the future – Startix 10).
Quartus Prime Pro Edition will reveal all the possibilities of Spectra-Q Engine, based on work with VLSI submarine capacity of several million equivalent logic elements (LE) and a clock frequency of the logical framework to 1 GHz. From the point of view of Quartus Prime UI does not differ substantially from the Quartus II.
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